The article presents a novel method for protecting analog Intellectual Property (IP) in Integrated Circuits (ICs) by utilizing layout-based effects. The technique exploits the impact of Length of Oxide Diffusion and Well Proximity Effect on transistors to fine-tune critical parameters. The method has been tested in two commercial CMOS technologies, a 28nm and a 65nm node. The results showed significant degradation in performance metrics when incorrect keys are employed, demonstrating the efficacy of the proposed technique. This research highlights the importance of securing analog components, which are often overlooked due to their smaller footprint within an IC.
Publication date: 12 Jan 2024
Project Page: https://arxiv.org/abs/2401.06508
Paper: https://arxiv.org/pdf/2401.06508
